1. Field of the Invention
The present invention relates to a semiconductor memory device of NOR type mask ROM, and more particularly to a semiconductor memory device realizing high speed access and high degree of integration, and a method of manufacturing the same.
2. Related art
FIG. 1 is a plan view showing an example of wiring pattern of a general flat NOR type mask ROM. That is, FIG. 1 is a plan view of a general cell layout of NOR type mask ROM having embedded digit lines. In a semiconductor substrate 1, a plurality of embedded digit lines 4 are arranged in stripes alternately with active regions 2. On the surface of the semiconductor substrate 1, moreover, a plurality of word lines 6 are arranged in stripes so as to cross perpendicularly with the embedded digit lines 4. The intersecting region of the active region 2 between the embedded digit lines 4 and the word lines 6, that is, the region enclosed by double dot chain lines in FIG. 1 corresponds to a unit memory cell MC. Herein, L refers to the channel length, and the W is the channel width. In this NOR type mask ROM, by implanting impurity ions of the same conductive type as the semiconductor substrate 1 selectively in the region of memory cell MC, the threshold value of the transistor of the memory cell MC can be changed, so that the data can be written in.
A conventional manufacturing method of the NOR type mask ROM shown in FIG. 1 will be explained below by referring to FIGS. 2A to 2D. FIGS. 2A to 2D are sectional views along line A--A in FIG. 1. First, as shown in FIG. 2A, an oxide film 303 is formed on a P type silicon substrate 301 (semiconductor substrate 1 in FIG. 1), and a photoresist film 307 is formed thereon, and further the photoresist film 307 is selectively removed from the region which becomes an embedded digit line 304 (digit line 4) in a later process, that is, the region sandwiching the active region 302, so that openings 307a are formed in stripes at specified intervals in the photoresist film 307.
Next, as shown in FIG. 2B, using the photo resist film 307 as mask, for example, arsenic is implanted as N type impurity in the P type silicon substrate 301, and embedded digit lines 304 are formed.
Then, after removing the photo resist film 307 and oxide film 303 consecutively, as shown in FIG. 2C, the surface of the P type silicon substrate 301 is oxidized, and a gate oxide film 305 made of silicon oxide film is formed on the surface of the P type silicon substrate 301.
Consequently, as shown in FIG. 2D, a polycrystalline silicon film is formed on the entire surface, and later, although not shown, the polycrystalline silicon film is selectively removed by the selective etching technology using the photo resist film, and stripes of word lines 306 (word lines 6 in FIG. 1) are formed perpendicular to the embedded digit lines 304.
In such conventional NOR type mask ROM, in order to enhancing the reading speed of data in the unit memory cells, it is preferred to lower the layer resistance of the embedded digit lines 304. For this purpose, it is essential to implant the N type impurity for forming the embedded digit lines 305 at high density. However, when the embedded digit line 304 is high in concentration, the junction capacity between the embedded digit line 304 and P type silicon substrate 301 increases, and the propagation speed in the embedded digit line 304 is lowered by the junction capacity. At the same time, the parasitic capacity between the embedded digit line 304 and word line 306 increases, and the propagation speed in the word line 306 is lowered.
To solve such problems, it has been proposed in Japanese Patent Application Laid-Open (JP-A) No. 5-259410 to form a groove at a region where an embedded digit line should be formed in the semiconductor substrate, embed the grooves with insulating region, and form impurity layers at the bottom and side wall of the groove to use as embedded digit lines. In this technique, since the embedded digit lines are formed in the bottom and side wall of the grooves, the parasitic capacity between the embedded digit line and word line can be reduced, and lowering of propagation speed in the word line can be prevented. It is, however, difficult to solve the contradictory problems of the lowering of resistance value of the embedded digit line and the lowering of the junction capacity between the embedded digit line and the semiconductor substrate. Yet, in such constituent of embedding the insulating region in the groove, the occupied area of the unit memory cell increases, which is a problem for realizing a high degree of integration.